Annual Target

• ~10 PDF reports with supporting images

Analysis Coverage

• Device metrics and salient features
• Package x-rays and die photos
• SEM plan-view images and cross-sectional SEM images
• Cross-sectional TEM images and material analysis

Analyst Curation

• Tri-annual analyst briefing
• Annual patent landscape summary
• Annual workshop

Real Time Update

• Access to project work in progress (PEF report, analyst briefing, etc.) before it is published

Process Flow Analysis (PFA)

• Reports showing process architecture, mask list, and integration-level process steps (target: 4 per year)

Process Flow Full Emulation (PFF)

• Expands upon the detail provided in PFA reports
• Layout GDS fully decomposed into process layers
• Provided PDF reports are built using Synopsys Process Explorer
• Manipulate report data in Synopsys (requires Synopsys license)
• Process Flow Full Emulation reports with supporting images (target: 4 per year)

Analyst

• Design technology interaction analysis
• Detailed explanation of process integration from wafer-in through wafer-out
• Process steps, materials, equipment type, unit process
• SEM and TEM cross-sectional and top-view images \ Layer annotations, specific process module, assumptions

• PDF Report
  • Company Profile
  • Executive Summary
  • Device Identification: Selected teardown photographs (optional), Package photographs, Package X-rays, Die photographs, including die corners and bond pad, and Delayered die photograph
  • Process Analysis: Die edge showing die thickness, Transistor gate array edge or Die Seal, Transistor gate array overview/detail
  • Layout Analysis: Annotated delayered die photograph, Die utilization table
  • Cost Analysis
• Folders of images
  • Package and Die images
  • SEM Cross Section images
• CircuitVision enabled top metal and gate level/substrate images
• ~15 reports / year

• PDF Report
  • Company Profile
  • Executive Summary
  • Device Identification: Selected teardown photographs (optional), Package photographs, Package X-rays, Die photographs, including die corners and bond pad, and Delayered die photograph
  • Process Analysis: Die edge showing die thickness, Transistor gate array edge or Die Seal, Transistor gate array overview/detail
  • Layout Analysis: Annotated delayered die photograph, Die utilization table
  • Cost Analysis
• Folders of images
  • Package and Die images
  • SEM Cross Section images
• CircuitVision enabled top metal and gate level/substrate images
• ~15 reports / year

Focused on leading edge power packaging technology, including SiC, GaN, Power Management ICs (PMIC), Intelligent Power Module, IGBT, Si MOSFETs, etc.

• PDF Report ( * Contents may vary depending on target devices )
  • Company Profile
  • Executive Summary
  • Product teardown overview
  • Package photographs and X-rays
  • Die photographs
  • Optical and SEM package cross-section analysis
  • SEM-EDS spectra of selected package materials
• Annual Target
  • ~10 PDF reports with supporting images
  • 8 hours of expert domain knowledge support
• Analyst
  • 2 analyst briefings per year

Focused on structural and materials analysis of PMICs found in marketing-leading linear regulators, switching regulators, voltage references, controllers, battery management ICs, etc. and spanning applications ranging from automotive, consumer, industrial, telecommunication, computing, medical and more.

The fundamentals of the Power subscription, Power Management IC (PMIC) Process Analysis provides:

• ID Images
  • Package photos and X-rays
  • Includes optical images at die level and gate level of PMIC (from backside poly images)
• Annotated die photo with sample locations (SEM, TEM etc)
  • Annotated images of gate level sample, detailing major circuit blocks e.g. logic, memory, power device etc
• SEM – Power transistor analysis
  • Plan view across bevel of the power transistor
  • Cross sections of the power transistor die (across the gates)
• SEM – control circuitry
  • Cross section of the controller region
• SEM-EDS – materials analysis results only, not the spectra
  • All present metal and dielectrics
• sMIM/SCM – Power transistor
  • Plan view across bevel of the power transistor
  • Cross sections of the power transistor region (across the gates)
• TEM
  • Cross-sections of power device gate oxide
  • Cross-section + TEM EDS of connecting regions such as vias, interfaces between metal layers and dielectric.
  • Cross-section of isolation region interfaces e.g. SOI, trench or deep doping wells
• Salient features and comparison summary slide
  • Dielectric layers composition & thickness
  • Metal layers composition & thickness
  • Critical feature horizontal & vertical dimensions

Schedule

• ~10 summary reports and hundreds of high-resolution supporting images/year
• Access to Work in Progress
• 3 Analyst Briefings/year
• 4 hrs expert support