Focused on embedded and emerging memory, provides a high level view of design quality by providing insight into memory area efficiency, the technology node for process generation, and memory capacity per die through functional analysis and benchmarking. Analysis may include process node and foundry identification, critical dimensions, functional block summary, stacked optical top metal and poly die photo delivered in CircuitVision^TM, SEM bevel and/or cross-sectional imaging

Focused on enabling understanding of all process aspects of embedded and emerging memory through dimensional, materials, architecture analysis. Also provides analyst perspective on the above to provide insight into trends and roadmap. Analysis may include SEM cross-sectional and bevel imaging, TEM cross-sectional with TEM EDS, technical trend/roadmap by technology element, interaction analysis, detailed explanation of process integrations and/or next node predictions

Requires a subscription to the Embedded & Emerging Process Analysis channel.

Provides insight into the manufacturing process steps, materials, and technology across leading edge embedded and emerging memory chips.

• Process Flow Analysis: Spreadsheets showing process architecture, mask list, and integration-level process steps
• Process Flow Full Emulation: Layout GDS fully decomposed into process layers, Synopsys Process Explorer PDF output reports, and/or Synopsys Input (Route-Level Deck) [Requires Synopsys license to view and modify]